NOR logic gate
A NOR logic gate can be implemented with the concatenation of an OR gate and a NOT gate, as shown in the following diagram.
It can be seen that, output X is a “logical 1”, only when all inputs are “logical 0”.
How to make a NOT gate with a NOR gate?
An interesting case of the NOR logic gate is that, like the NAND gate, when the inputs are joined, to form a single input, the output (X) has exactly the opposite value of the input.
See the two columns of the previous truth table. The output is the inverse of the input.