NAND gate using transistors
This NAND gate using transistors circuit simulates the operation of a two or more inputs NAND gate. (There is a diode for each input. D1, D2, D3, …, Dn)
How the NAND gate using transistors works?
The truth table below shows the behavior of a NAND gate. We can see that the output is a logic “Low” when all inputs are in “High” logic level.
Any other combination of inputs (“Low” and “High”) will cause the output to have a “High” logic level. The diagram shows that the circuit uses two transistors, working in the cut-off and saturation regions.
In the case when both inputs are “High” logic level, the two diodes are inversely polarized and they behave like an open circuit. The transistor Q1 is biased through resistor R1 and enters the saturation region. The saturation current of transistor Q1 biases the Q2 transistor. The Q2 transistor goes into saturation, causing a “Low” logic level at the output (collector Q2).
If any or all inputs are logic “Low”, the base of the transistor does not have enough voltage to be polarized and transistor Q1 does not conduct. Without the collector current of Q1, transistor Q2 is not biased, there is no current conduction and the output will be a “high” logic level.
Note: The circuit is powered by 5 volts.
List of circuit components
- Q1 = Q2: 2N2222 NPN transistors or equivalent
- D1 = D2 = D3 = …. Dn: semiconductor diode 1N914 or equivalent
- R1: 2.2K resistor
- R2: resistor 470 ohms
- R3: 47K resistor
- R4: 2.7K resistor